The keys to ensuring IC quality

ICs need to meet a level of quality that ensures that the products work correctly for its given lifecycle. As measured by the number of defects found during manufacturing test, quality can vary significantly depending on a device’s target market. If you are designing SoCs for automotive, aerospace or medical, then the process covering design, manufacturing, test, and in-life monitoring can be quite difficult. The challenges involved range from adherence to standards and regulations, managing capital investments and engineering resources, securing the right tools and flows, and establishing methods to manage the vast amounts of data that inform each step in the lifecycle of the device.

Why focus on IC quality

IC quality is made up of several parts. Some of the key components are:

• How well a chip functions,
• How reliable it is,
• How safe and secure it is, and
• How thoroughly it is tested for physical defects and potential latent or future defects.

Quality affects the bottom line: lower quality chips don’t yield as well, generate more field returns, and lead to disappointing performance. Defects that are missed or occur in early life also affect the bottom line significantly.

Making ICs for the fast-growing automotive market presents challenges across the entire design flow. To meet the ISO 26262 standard and accomplish the goal of zero defective parts per million (DPPM) for manufacturing test, design for test (DFT) engineers have embraced new test pattern types, including cell-aware, interconnect, and inter-cell bridge (cell neighborhood). But the traditional methods of choosing the types of patterns to apply and setting coverage targets is leaving improvements to quality, test time, and test cost on the table.

Factors in testing for high quality ICs

DFT engineers set target metrics for automatic test pattern generation (ATPG) and choose the best set of patterns to target different faults. Test coverage targets for static and dynamic patterns targeting, respectively, stuck-at and transition fault models are usually based on the percentage of faults detected. These targets vary by company, and it often takes years of production fail data to decide on appropriate goals. When a company moves to a new process node or needs to add a new fault model, the target could become completely different than test coverage based on the full fault list. For example, consider targeting test coverage for all potential bridge faults — this could be a huge list. You might achieve 99 percent detection of all bridge faults but miss hundreds of the most likely bridges. To reduce DPPM, it is more effective to choose the subset of bridges that is most likely to occur.

How to improve IC quality with critical area-based test pattern optimization

Newer methods of scan testing offer unique production defect detections. One approach to measuring pattern value provides a consistent, ‘apples to apples’ assessment of patterns to detect defects based on the likelihood of the physical defects occurring. In other words, first determine the likelihood of defects occurring based on their critical area, then you can sort the various pattern sets, considering the defects they detect, to choose the most effective patterns to apply.

Total critical area (TCA) provides a common metric to assess a pattern’s impact on defective parts per billion (DPPB). This is useful for sorting or ordering patterns to achieve the lowest DPPB for a given number of patterns. As a result, you can mix in patterns targeting new fault models for a more effective pattern set, even with the same number of patterns as your original pattern set. You can select or sort the most effective patterns from your entire pattern set based on their ability to detect physical defects.

Pattern selection and ordering based on TCA provides a faster coverage ramp, based on the likelihood to detect physical defects compared to traditional approaches.

The automatic test pattern generation (ATPG) tool calculates TCA values using physical layout information. A user-defined fault model (UDFM) file stores the models for each defect type (cell-internal, bridge, open, cell-neighborhood). Anyone using cell-aware or automotive-grade ATPG will be familiar with UDFM files. Just load the UDFM files into the ATPG tool to generate test patterns and for use in layout-aware and cell-aware failure diagnosis. In the ATPG tool, you can apply the UDFM files containing TCA fault data to patterns to sort them from highest TCA to lowest.

Features of using TCA include:

• Selecting the most effective patterns;
• Choosing targets for pattern types and coverage;
• Determining the effectiveness of new pattern types;
• Grading pattern value by likelihood to detect defects;
• Automatically sorting and selecting patterns; and
• Creating a smaller pattern set by targeting multiple fault models in our ATPG run.

The importance of high-quality fault models

Underlying the effectiveness of TCA is a toolbox of high-quality fault models, which are also referred to as automotive-grade ATPG. The models include:

Cell-aware: Also called cell-internal, this fault model targets physical defects that can occur within the technology standard cell. The cell library physical design is characterized to produce a user-defined fault model (UDFM) used by ATPG. Cell-aware test models the following types of defects:

• Port open: A disconnected port.
• Port bridge: A bridge between a port and VSS, VDD, or any other port of the cell.
• Bridge: Any cell-internal bridge defect, such as bridges between adjacent objects in the same layer or different layers. In the case of non-layout-aware runs, bridges are calculated based on parasitic capacitors in the SPICE netlist.
• Open: Any cell-internal open defect, such as an open in poly, metal, diffusion, or vias. In the extracted SPICE netlist, the tool matches these defects to existing parasitic resistors by increasing their resistance values.
• Ton: Any cell-internal transistor defect that switches a transistor partially on with a specific resistive value.
• Toff: Any cell-internal defect that switches a transistor partially off with a specific resistive value.

Interconnect: Any bridge or open defect in the interconnect.

Inter-cell bridge:  Also called cell neighborhood defects, these are chip-dependent bridge defects located at the interface between one instance of a standard cell and a neighboring cell. Such defects can occur between cell-internal nets (layers) not directly accessible from the cell interconnect nets.

Pattern selection, grading and sorting based on critical area

DFT engineers can compare patterns for multiple fault models and select the most effective using a consistent and realistic metric. The only restriction is that fault models for static and dynamic patterns must be sorted separately.

Figure 1 shows how to load various fault models to optimize your pattern set. Use these models to simulate and calculate the TCA for an existing pattern set or to create a new pattern set from scratch. The ATPG tool will generate reports showing the TCA included during ATPG, summary coverage, fault list, and a layer-based TCA summary.

Once you create UDFM files with TCA data for the various fault models, you can grade and sort any existing pattern set based on TCA. This is true even for patterns created without any TCA considerations, such as stuck-at patterns. The steps to sort existing patterns based on TCA are:

1. Load the UDFM files for the various fault models that you want to use.
2. Load the existing pattern sets.
3. Simulate the patterns using TCA from UDFMs.
4. Sort the patterns.

Figure 1. The separate UDFM files can be read in to order and optimize the combined patterns based on TCA (Siemens EDA)

Use packetized test data delivery over a bus-based network

The packetized delivery of scan test patterns is proving to be a once in a decade advance in DFT technology for complex designs, particularly those demanding high quality. It enables simultaneous testing of any number of cores with few chip-level pins, plus reduces test time and test data volume, as shown in Figure 2. With the Tessent Streaming Scan Network (SSN) from Siemens, DFT engineers have a true SoC DFT solution without compromises between implementation effort and manufacturing test cost. The inclusion of SSN also vastly reduces the overall DFT architecture complexity so also reduces over all time to market.

Figure 2. Tessent Streaming Scan Network distributes packetized scan test data to multiple cores across a synchronous bus (Siemens EDA)

High-quality test for 2.5D and 3D designs

Chiplets integrated on a common interposer (2.5D) or stacked on top of each other (3D) have special considerations for quality that DFT addresses. For 3D IC logic test, we have these high-level considerations:

• Full test of individual die at wafer level because some die pins are not available for probe by automatic test equipment (ATE).
• Choose a technology to efficiently perform die-to-die test in the package. The interposer for 2.5D and through-silicon vias (TSV) or micro bumps for 3D stacking are examples of methods for inter-die connection. These die-to-die connections must also support a repair mechanism to help recover yield loss.
• Choose how to access any die(s) in the package for sufficient tests.
• Automate failure diagnosis for inter-die and intra-die failures.

Fully testing die at the wafer level is a matter of high test coverage using advanced fault models. Including only known-good die in a stack is a major requirement of successful 2.5D and 3D packages. But it’s not the only one.

Specialize software can automate test for 2.5D and 3D designs through execution of the IEEE 1838 standard. Tessent Multi-die, for example, ensures compliance with the standard, which is crucial to support the multiplex of collective dies stacked into a package (Figure 3).

Figure 3. A schematic overview of IEEE 1838 for 3D test (IEEE/Siemens EDA)

The role of diagnosis and failure analysis

DFT does not end with detecting manufacturing defects. It also works to improve the manufacturing process and increase yield, which has a direct impact on business. Manufacturing test collects a massive amount of data from failing tests, revealing valuable information about the mechanisms that cause a circuit to fail. Designers and product engineers can analyze this data through scan diagnosis to find the true causes and locations of circuit failures. Scan diagnosis improves the success of physical failure analysis used to validate the defect mechanism.

Fixing a systematic yield problem requires data about the failure mechanisms on an entire population of failing die across wafers and lots. Performing volume scan diagnosis, an advanced technique that uses statistics and machine learning, speeds yield ramp for new processes and improves yield for mature processes. This technology is in use at many successful companies.

This underlines the importance of finding a good software tool for volume scan diagnosis that leads to improved IC quality. One recent solution is a partnership between Tessent’s diagnosis solution and PDF Solutions to improve yield ramp and solve yield limiters through volume manufacturing (Figure 4).

Figure 4. Layout pattern, diagnosis and root-case deconvolution (RCD) flow with Tessent and PDF Solutions (Siemens EDA/PDF Solutions)

Summary

Achieving target quality metrics in today’s chips requires careful planning throughout the design process. DFT is critically important for manufacturing high-quality silicon and Tessent offers industry-leading solutions that help designers efficiently meet their quality goals.

About the author

Lee Harrison is Director, Product Marketing, at Siemens EDA’s Tessent Division.